1. Introduction to Verilog HDL
  2. Data types
  3. Operators
  4. Data flow modeling
  5. Gate-Level modeling
  6. Behavioral modeling
  7. Modeling timing and delays
  8. Parameters, tasks and functions
  9. Compiler directives
  10. System tasks
  11. File input/output
  12. Switch-level modeling
  13. User Defined Primitives