Course Outline:

In depth coverage on Industry Required Skills,

Focus on building core skills in ASIC Design & Verification,

Complte Front End Design & Verification using Verilog + systemvterilog + UVM + IP / SoC Level verification with Industry standard protocols

Training Descriptions:

1. For Interested Candidates conduct the Training on GreenSilicon at Bangalore, India.

2. The focus area of activities would be Verification/ VIP/ Test Environment development in System Verilog/ UVM environment following domain SPI, Ethernet, UART, AHB, APB, USB, AXI, LC3 with Industry Protocols.

3. The training will be taken through hands-on training in Verification methodologies such as UVM and in the respective domain. Subsequent to training, the nature of work would be on the following lines:

4. Understanding IP/SoC architecture for VIP or Test environment, coding in one of the HVL such as System Verilog

5. UVM Verification of the blocks that are coded, understanding and implementing functional Verification infrastructure. It will involve closely working as part of the IP/SoC Verification IP development.

Who will benefit from this Course?

  • VLSI Verification Engineers having knowledge in Verilog/VHDL and willing to jump up their career with System Verilog / UVM skillset.
  • VLSI Engineers working in other areas (such as FPGA, STA, Design, etc), and willing to broaden their skills and explore opportunities to further grow up their career.
  • Fresher’s or Electronics students interested in pursuing VLSI Verification as career


  • B.E / B.Tech / M.E / M.Tech with background in Electronics, should have minimum aggregate of 60% throughout academic career
  • Basic knowledge in Verilog
  • Good knowledge on Digital design
  • Good knowledge on any Processor architectures
  • Good logical & analytical ability

Admission Procedure

All the eligible interested candidates have to go through formal written test followed by personal interview. Written test format is composed of Digital, Processor architecture, Analytical and Logical questions. Please walkin/mail/call us to schedule for written test & personal interview. Outstanding performers in the test may be awarded with partial / full scholarships.

Working professionals in any stream will get direct admission to this program, they need not appear for any written test / personal interview. However, they need to submit the State of Purpose to take up the course.

Grading & Certifications

All the participants who fulfilled course assignments, case studies and final exams would be awarded with “Advanced Certification in SoC Verification using System verilog / UVM”

Placement Assistance

All the eligible participants who have fulfilled requirements of the course will be given 100% placement assistance through our dedicated placement cell. As a part of the placement process, all the participants were assisted with preparing professional resume.

For Admission Send email to for course registration and fee details